High-Speed Multilayer PCB Stackup, IPC-2141 Symmetric Stripline & Signal Integrity
Symmetric Stripline PCB Impedance Z0 & Delay Formula
Calculate Single-Side Dielectric Height h = (b - t)/2 (mm), IPC-2141 Symmetric Stripline Characteristic Impedance Z0 (ohms), Pure TEM Propagation Delay (ps/mm), and Line Capacitance (pF/cm).
Unlike outer-layer microstrip, buried inner-layer stripline is sandwiched between TWO ground planes—giving pure TEM propagation at full SQRT(Dk)!
Routing DDR5 / PCIe Gen5 signals on an inner PCB layer centered symmetrically inside Plane-to-Plane Spacing `b` (mm, so core/prepreg thickness above and below copper thickness `t` is `h = (b - t) / 2`) surrounds the trace completely in homogeneous laminate Dielectric Constant `epsilon_r` (`Dk`) with ZERO air-boundary fringing! Consequently, Effective Dielectric Constant equals bulk `epsilon_r` directly (making inner-layer stripline propagation `~15%` SLOWER than outer-layer microstrip on the exact same board: `t_pd = (SQRT(epsilon_r) / 299.792458) * 1,000` ps/mm!), eliminates far-end inductive/capacitive modal crosstalk skew (`FEXT ≈ 0`!), and obeys the IPC-2141 / Cohn Symmetric Stripline Impedance formula `Z_0 = (60 / SQRT(epsilon_r)) * LN((1.9 * b) / (0.8 * w + t))` ohms, with Intrinsic Capacitance `C_0 = (t_pd_ps_mm * 10) / Z_0` pF/cm!
Verify on a 50-Ohm Multilayer FR-4 Inner-Layer Stackup—Plane_to_Plane_Spacing `b` = 0.420 mm (B2), Inner_Trace_Width `w` = 0.140 mm (`5.5` mil, B3), `1`-oz Copper_Thickness `t` = 0.035 mm (B4 -> Single Dielectric Height `h = 0.1925` mm in E2), and Laminate_Dk `epsilon_r` = 4.10 (B5): Symmetric Stripline Impedance `Z_0` hits `50.13` ohms (E3), Pure-TEM Flight Delay equals `6.754` ps/mm (`171.6` ps/in, E4), and Line Capacitance equals `1.347` pF/cm (E5)!
| IPC-2141 Symmetric Stripline KPI (b=0.42 mm, w=0.14 mm, t=0.035 mm, Dk=4.10) | Formula | Verified Output |
|---|---|---|
| Half-Dielectric Spacing h (mm) | (Plane_Spacing_b - Copper_t) / 2 | 0.1925 mm |
| Characteristic Impedance Z0 (ohms) | (60/SQRT(er)) * LN((1.9*b)/(0.8*w + t)) | 50.13 ohms (55.05 ohms @ Megtron 3.4) |
| Pure-TEM Flight Delay (ps/mm) | (SQRT(Dielectric_er) / 299.792458) * 1000 | 6.754 ps/mm (6.151 ps/mm @ Dk = 3.4) |
| Distributed Capacitance (pF/cm) | (Delay_ps_mm * 10) / Impedance_Z0 | 1.347 pF/cm (1.117 pF/cm @ Dk = 3.4) |
IPC-2141 Symmetric Stripline Impedance, TEM Delay & Capacitance Formula
Validate `Plane_Spacing b > 2 * t`, `Trace_Width w > 0`, `Copper_Thickness t > 0`, `(0.8 * w + t) < b` (so `LN` stays positive and physical!), and `Dielectric_Dk` in `[1.8, 12.0]`!
=LET(bs_m, B2, wt_m, B3, tc_m, B4, er_d, B5, IF(OR(tc_m <= 0, wt_m <= 0, bs_m <= 2 * tc_m, (0.8 * wt_m + tc_m) >= bs_m, er_d < 1.8, er_d > 12), "Invalid Stripline Input", LET(zo_h, (60 / SQRT(er_d)) * LN((1.9 * bs_m) / (0.8 * wt_m + tc_m)), td_p, (SQRT(er_d) / 299.792458) * 1000, ROUND((td_p * 10) / zo_h, 3))))Low-Loss Megtron-6 (Dk = 3.40) Laminate Substitution Check (Set Dk B5 = 3.40)
Re-spin the board on ultra-low-loss Megtron-6 laminate (`Dk` B5 = 3.40) without re-tuning copper width `w`: Stripline Impedance E3 rises `+4.92` ohms to `55.05` ohms, Flight Delay E4 speeds up by `9%` to `6.151` ps/mm, and Distributed Capacitance E5 drops to `1.117` pF/cm!
=IF(ISTEXT(E5), E5, ROUND((60 / SQRT(B5)) * LN((1.9 * B2) / (0.8 * B3 + B4)), 2))Try the example
Use the original values or change them to test your understanding.