High-Speed PCB Design, RF/SerDes Controlled Impedance & IPC-2141 Microstrip Lines
Microstrip PCB Impedance (Z0) & Propagation Delay Formula
Calculate Quasi-TEM Effective Dielectric Constant epsilon_eff, IPC-2141 Microstrip Characteristic Impedance Z_0 (Ohms), Propagation Delay (ps/mm), and Phase Velocity (% of c).
Why outer-layer microstrip signals travel FASTER than inner stripline—because electric field lines share FR-4 and air!
A surface Microstrip PCB trace of width W (mm) and copper thickness T (mm) separated by prepreg height H (mm) above an unbroken ground plane launches electromagnetic waves partly inside the substrate (`epsilon_r ~= 4.20` for high-Tg FR-4) and partly through air above solder mask (`epsilon_air = 1.00`)! Hammerstad’s quasi-TEM field-sharing formula gives Effective Dielectric Constant epsilon_eff = ((epsilon_r + 1) / 2) + ((epsilon_r - 1) / 2) * (1 / SQRT(1 + 12 * (H / W))), while IPC-2141’s closed-form design equation yields Characteristic Impedance Z_0 = (87 / SQRT(epsilon_r + 1.41)) * LN((5.98 * H) / (0.8 * W + T)) Ohms! Because epsilon_eff (~3.15) is substantially lower than bulk FR-4 (4.20), outer microstrip signals propagate faster at Time-of-Flight Delay t_pd = 3.33564 * SQRT(epsilon_eff) ps/mm (~5.92 ps/mm vs ~6.84 ps/mm on internal stripline—critical when length-matching DDR5 byte lanes across layers)!
Verify on a 4-Layer RF / PCIe Stackup—Trace_Width W = 0.26 mm (B2), Prepreg_Height H = 0.16 mm (B3), Finished_Copper_Thickness T = 0.035 mm (1-oz outer, B4), and Substrate_Dielectric_Constant epsilon_r = 4.20 (B5): Effective Dielectric Constant lands at 3.153 (E2), Microstrip Characteristic Impedance Z_0 hits 50.34 Ohms (right inside the 50 +/- 10% Ohm RF target!, E3), Propagation Delay equals 5.92 ps/mm (E4), and Signal Velocity reaches 56.32% of vacuum light speed c (E5)!
| IPC-2141 Microstrip KPI (W=0.26 mm, H=0.16 mm, T=0.035 mm, FR-4 Er=4.20) | Formula | Verified Output |
|---|---|---|
| Effective Permittivity eps_eff | (Er+1)/2 + ((Er-1)/2)/SQRT(1 + 12*H/W) | 3.153 (3.327 @ wide W = 0.50 mm) |
| Characteristic Impedance Z0 (Ohm) | (87/SQRT(Er+1.41)) * LN(5.98*H/(0.8*W+T)) | 50.34 Ohms (28.95 Ohms @ W = 0.50) |
| Propagation Delay tpd (ps/mm) | 3.33564 * SQRT(eps_eff) | 5.92 ps/mm (6.08 ps/mm @ W = 0.50) |
| Phase Velocity (% of Vacuum c) | (1 / SQRT(eps_eff)) * 100 | 56.32% c (54.82% c @ W = 0.50 mm) |
IPC-2141 Microstrip Impedance Z0 & Quasi-TEM Delay Formula
Validate W > 0, H > 0, T >= 0, Substrate epsilon_r in [1.8, 12.0], and geometry inside the logarithmic validity bound (5.98 * H > 1.2 * (0.8 * W + T))!
=LET(wd_m, B2, ht_m, B3, tk_m, B4, er_s, B5, IF(OR(wd_m <= 0, ht_m <= 0, tk_m < 0, er_s < 1.8, er_s > 12, (5.98 * ht_m) <= 1.2 * (0.8 * wd_m + tk_m)), "Invalid Microstrip Geometry", LET(ef_e, ((er_s + 1) / 2) + ((er_s - 1) / 2) * (1 / SQRT(1 + 12 * (ht_m / wd_m))), ROUND((1 / SQRT(ef_e)) * 100, 2))))Low-Impedance Capacitive Pad / Wide-Bus Mismatch Check (Set Trace Width W = 0.50 mm)
Widen Trace_Width B2 from 0.26 mm to 0.50 mm over the same 0.16 mm prepreg: more electric field concentrates inside FR-4 (epsilon_eff E2 rises to 3.327) while Characteristic Impedance Z_0 E3 plunges from 50.34 Ohms down to 28.95 Ohms—creating a strong capacitive reflection discontinuity!
=IF(ISTEXT(E5), E5, ROUND((87 / SQRT(B5 + 1.41)) * LN((5.98 * B3) / (0.8 * B2 + B4)), 2))Try the example
Use the original values or change them to test your understanding.