CMOS Digital Design & Low-Power Electronics
Sakurai Alpha-Power CMOS Delay & EDP Formula
Calculate CMOS Dynamic Switching Energy E_dyn = C_L * V_DD^2, Sakurai Velocity-Saturated Propagation Delay t_p = 0.5 * C_L * V_DD / (K_d * (V_DD - V_th)^alpha), Shockley Square-Law Bias, and Energy-Delay Product (EDP).
Stop modeling short-channel FinFET/nanosheet gates with Shockley’s alpha = 2 square law!
Textbook long-channel Shockley MOSFET equations assume drain saturation current scales quadratically with gate overdrive: I_Dsat = K_d * (V_DD - V_th)^2. In nanometer FinFET and gate-all-around (GAA) nodes, high lateral channel electric fields saturate carrier velocity, flattening saturation current toward a LINEAR power law! T. Sakurai and A.R. Newton (1990, IEEE Journal of Solid-State Circuits) introduced the industry-standard Alpha-Power Law model (1 <= alpha <= 2, with alpha ~ 1.0–1.3 in modern velocity-saturated silicon): 50% inverter propagation delay in picoseconds is t_p50 = 0.5 * (C_L_fF * V_DD) / (K_drv * (V_DD - V_th)^alpha), Dynamic Switching Energy is E_dyn = C_L_fF * V_DD^2 (fJ), and Energy-Delay Product is EDP = E_dyn * t_p50 (fJ*ps)!
Verify on Supply_Voltage V_DD = 1.00 V (B2), Threshold_Voltage V_th = 0.20 V (0.80 V overdrive, B3), Velocity_Saturation_Alpha = 1.00 (B4), Load_Capacitance C_L = 16.0 fF (B5), and Drive_Coeff K_drv = 0.50 mA/V^alpha (B6): Dynamic Switching Energy is 16 * 1.0^2 = 16.00 fJ (E2); Sakurai 50% Gate Delay is 0.5 * 16.0 / (0.50 * 0.80^1.0) = 20.00 ps (E3), whereas long-channel Shockley alpha = 2 predicts 8.0 / 0.32 = 25.00 ps (E4); and Energy-Delay Product is 16.00 * 20.00 = 320.00 fJ*ps (E5)! Undervolt V_DD to 0.60 V (B2 = 0.60): Sakurai delay rises modestly by +20% to 24.00 ps while EDP plunges 56.8% to 138.24 fJ*ps—whereas Shockley square-law falsely predicts a 60.00 ps timing failure!
| CMOS Gate Timing Metric (VDD=1.0V, Vth=0.2V, alpha=1.0, CL=16fF, Kd=0.50) | Formula | Verified Output |
|---|---|---|
| Dynamic Switching Energy (fJ) | C_L_fF * V_DD^2 | 16.00 fJ (5.76 fJ @ 0.60V) |
| Sakurai 50% Gate Delay (ps) | 0.5 * C_L * V_DD / (K_d * (VDD - Vth)^alpha) | 20.00 ps (24.00 ps @ 0.60V) |
| Shockley alpha=2 Delay (ps) | 0.5 * C_L * V_DD / (K_d * (VDD - Vth)^2) | 25.00 ps (60.00 ps @ 0.60V!) |
| Energy-Delay Product EDP (fJ*ps) | E_dyn * t_p50 | 320.00 fJ*ps (138.24 @ 0.60V) |
Sakurai Alpha-Power Propagation Delay Formula
Guard V_DD <= V_th (subthreshold leakage regime where strong-inversion overdrive vanishes) and constrain 1 <= alpha <= 2!
=LET(v_dd, B2, v_th, B3, al_p, B4, c_ld, B5, k_dr, B6, IF(OR(v_dd <= 0, v_th < 0, al_p < 1, al_p > 2, c_ld <= 0, k_dr <= 0), "Invalid CMOS Parameter", IF(v_dd <= v_th, "Subthreshold Cutoff (VDD <= Vth)", ROUND((0.5 * c_ld * v_dd) / (k_dr * ((v_dd - v_th) ^ al_p)), 2))))Dynamic Voltage Scaling (DVS) Energy-Delay Product Formula
Evaluate EDP = E_dyn * t_p50 across V_DD sweeps during RTL power-performance-area (PPA) peer review!
=IF(ISTEXT(E3), E3, ROUND(E2 * E3, 2))Try the example
Use the original values or change them to test your understanding.