Electronics Thermal Management, Exposed-Pad QFN/MOSFET Cooling & Plated Thermal Vias
PCB Thermal Via Array Resistance & Temperature Rise Formula
Calculate Hollow Plated-Copper Barrel Ring Area (mm²), Single-Via Vertical Thermal Resistance (°C/W), Parallel N-Via Array Resistance (°C/W), and Exposed-Pad Board Delta_T (°C).
Modeling a plated PCB via as a solid copper rod underpredicts thermal resistance by 3.3x—because the barrel is a hollow 25-micron cylinder!
Exposed-pad QFN MOSFETs, GaN FETs, and linear regulators sink heat vertically through a 1.60 mm FR-4 board into bottom ground planes via a grid of N plated through-hole Thermal Vias! Beginners mistakenly plug full drill diameter D_drill into `PI()*r_o^2`, forgetting that standard PCB electroless/electroplated holes deposit only ~25 micrometers (0.025 mm) of copper wall inside outer radius r_o = D_drill / 2, leaving hollow inner radius r_i = r_o - (t_Cu_um / 1,000) filled with air or low-conductivity epoxy! Exact Copper Annular Ring Area is A_Cu = PI() * (r_o^2 - r_i^2) mm² (~0.0216 mm² on a 0.30 mm drill vs 0.0707 mm² solid!), giving Single-Via Fourier Conduction Resistance R_th,1 = (Board_H_mm / 1,000) / (k_Cu * (A_Cu * 10^-6)) °C/W (~192 °C/W per via!), Parallel Array Resistance R_th,array = R_th,1 / N, and Through-Board Temperature Drop Delta_T = P_diss * R_th,array!
Verify on a 3.5 W Power-IC Exposed Thermal Pad with a 4x4 (16-Via) Grid—Finished_Drill_OD D_d = 0.30 mm (B2), Barrel_Copper_Plating t_Cu = 25.0 um (B3 -> Copper Ring Area = 0.0216 mm² in E2), PCB_Thickness H = 1.60 mm (B4), Parallel_Via_Count N = 16 (B5), Copper_Thermal_Conductivity k_Cu = 385.0 W/(m·K) (B6), and IC_Power_Dissipation P = 3.50 W (B7): Single-Via Thermal Resistance hits 192.41 °C/W (E3), 16-Via Parallel Array Resistance drops to 12.03 °C/W (E4), and Through-Board Pad Delta_T equals 42.09 °C (E5)!
| PCB Thermal Via Grid KPI (0.30 mm Drill, 25 um Cu, 1.6 mm PCB, 16 Vias, 3.5 W) | Formula | Verified Output |
|---|---|---|
| Plated Copper Ring Area (mm²) | PI() * ((D/2)^2 - (D/2 - t_um/1000)^2) | 0.0216 mm² |
| Single-Via Resistance Rth,1 (°C/W) | (Board_H_m) / (k_Cu * Ring_Area_m2) | 192.41 °C/W |
| N-Via Parallel Array Rth (°C/W) | R_th_Single / Via_Count_N | 12.03 °C/W (5.34 °C/W @ 6x6 = 36 vias) |
| Through-Board Pad Delta_T (°C) | Power_W * R_th_Array | 42.09 °C (18.71 °C @ 36 vias!) |
Hollow Plated-Barrel Fourier Thermal Resistance & Parallel Array Formula
Validate Drill_OD > 0.10 mm, Plating t_Cu > 5 um with 2 * (t_Cu / 1000) < Drill_OD, Board_Thickness > 0, Via_Count N >= 1, k_Cu > 50 W/(m·K), and Power >= 0!
=LET(dd_m, B2, cu_u, B3, bh_m, B4, nv_c, B5, kc_u, B6, pd_w, B7, IF(OR(dd_m <= 0.1, cu_u <= 5, (2 * cu_u / 1000) >= dd_m, bh_m <= 0, nv_c < 1, kc_u <= 50, pd_w < 0), "Invalid Thermal Via Input", LET(ro_m, dd_m / 2, ri_m, ro_m - (cu_u / 1000), ar_g, PI() * ((ro_m ^ 2) - (ri_m ^ 2)), rs_v, (bh_m / 1000) / (kc_u * (ar_g * 0.000001)), ROUND(pd_w * (rs_v / nv_c), 2))))Dense 6x6 (36-Via) Exposed-Pad Array Upgrade Check (Set Via Count N = 36)
Pack a tighter 6x6 grid of N B5 = 36 thermal vias under the QFN exposed pad: Parallel Array Thermal Resistance E4 drops from 12.03 °C/W down to 5.34 °C/W, slashing Through-Board Temperature Drop E5 more than half from 42.09 °C down to 18.71 °C!
=IF(ISTEXT(E5), E5, LET(ro_m, B2 / 2, ri_m, ro_m - (B3 / 1000), ar_g, PI() * ((ro_m ^ 2) - (ri_m ^ 2)), rs_v, (B4 / 1000) / (B6 * (ar_g * 0.000001)), ROUND(rs_v / B5, 2)))Try the example
Use the original values or change them to test your understanding.