Computer Architecture & Thermal Chip Design
Dennard Scaling Breakdown & Dark Silicon Formula
Calculate Full-Chip Unthrottled Dynamic Power alpha * C_nF * V_DD^2 * f_GHz, Total Unthrottled Die Power, Thermal Design Power (TDP) Active Lit-Silicon Fraction, and Power-Gated Dark Silicon Share.
Quantify why post-Dennard voltage floors force modern SoCs to power-gate Dark Silicon!
Under Robert Dennard’s 1974 constant-electric-field MOSFET scaling law, shrinking linear transistor dimensions by 1/kappa reduced capacitance C by 1/kappa AND supply voltage V_DD by 1/kappa while raising clock frequency f by kappa—keeping areal power density (kappa^2 * C * V_DD^2 * f) strictly constant! Around 2005, subthreshold leakage prevented V_DD from scaling below ~0.7–0.8 V. As Esmaeilzadeh et al. (2011, ISCA "Dark Silicon and the End of Multicore Scaling") demonstrated, once All-Tiles-Active Power P_full = alpha_sw * C_tot_nF * V_DD^2 * f_GHz + P_leak_full exceeds package cooling Thermal Design Power (TDP_cap), the chip can illuminate at most Active Fraction phi_lit = MIN(1, TDP_cap / P_full), leaving Dark_Silicon_Share = 1 - phi_lit power-gated off at any microsecond!
Verify using exact SI scaling (1 nF * 1 V^2 * 1 GHz = 1 Watt!) on Total_Chip_Capacitance C_tot = 250 nF (B2), Activity_Factor alpha_sw = 0.20 (B3), Supply_Voltage V_DD = 0.80 V (B4), Boost_Clock f = 5.0 GHz (B5 -> Full Dynamic Power = 0.20 * 250 * 0.64 * 5.0 = 160.00 W in E2), Full_Die_Leakage P_leak = 40.0 W (B6 -> All-Tiles Power = 200.00 W in E3), and Package_TDP_Cap = 100.0 W (B7): Maximum Lit Silicon Fraction is 100 / 200 = 0.5000 (E4), forcing 50.00% Dark Silicon (0.5000 in E5)!
| Post-Dennard Thermal Metric (C=250nF, alpha=0.20, VDD=0.8V, f=5GHz, Pleak=40W, TDP=100W) | Formula | Verified Output |
|---|---|---|
| Unthrottled Dynamic Power (W) | alpha_sw * C_nF * V_DD^2 * f_GHz | 160.00 W (32.00 W @ 1 GHz) |
| Full-Chip All-Tiles-On Power (W) | P_dynamic_full + P_leak_full | 200.00 W (300.00 W next node) |
| Active Lit-Silicon Fraction | MIN(1, TDP_Cap / P_full) | 0.5000 (50.00% Lit Area) |
| Power-Gated Dark Silicon Share | 1 - Active_Lit_Fraction | 0.5000 (0.6667 next node; 0 @ 1 GHz) |
Post-Dennard Dark Silicon Fraction Formula
Validate C_tot > 0, 0 < alpha_sw <= 1, V_DD > 0, f_GHz > 0, P_leak >= 0, and TDP_Cap > 0!
=LET(c_nf, B2, al_s, B3, v_dd, B4, f_gh, B5, p_lk, B6, td_p, B7, IF(OR(c_nf <= 0, al_s <= 0, al_s > 1, v_dd <= 0, f_gh <= 0, p_lk < 0, td_p <= 0), "Invalid CMOS Power Envelope", LET(p_fl, al_s * c_nf * (v_dd ^ 2) * f_gh + p_lk, ph_l, MIN(1, td_p / p_fl), ROUND(1 - ph_l, 4))))Next-Node Density Scaling vs Underclocked Mobile Sweep
Test scaling transistor count at fixed V_DD = 0.8V (C_tot = 350 nF, P_leak = 76 W -> P_full = 300 W, Dark Silicon rises to 0.6667 = 66.67%) vs downclocking to f = 1.0 GHz & P_leak = 20 W (P_full = 52 W <= 100 W TDP -> 0.0000 Dark Silicon)!
=IF(ISTEXT(E3), E3, ROUND(MIN(1, B7 / E3), 4))Try the example
Use the original values or change them to test your understanding.